The present invention is generally directed to semiconductor structures, and more particularly to a semiconductor structure having electrically conductive probes extending from a backside of the semiconductor structure to selected regions in the substrate of the semiconductor structure.
During manufacture of an integrated circuit, electronic components are formed upon and within a front side surface of a semiconductor structure having opposed front side and backside surfaces. The components are inter-coupled with electrically conductive interconnect lines to form an electronic circuit. Signal lines that are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit, or xe2x80x9cchip,xe2x80x9d is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. The I/O pads of the chip are electrically connected to the terminals of the device package. Some types of device packages have terminals called xe2x80x9cpinsxe2x80x9d for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called xe2x80x9cleadsxe2x80x9d for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip increases, however, the number of signal lines that need to be coupled to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. Constraints of high-volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. Mishandling can result in a loss of lead co-planarity, adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high frequency electrical performance of larger peripheral-terminal device packages suffers as a result.
Grid array semiconductor device packages have terminals arranged in a two-dimensional array across an underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal lines from chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (xe2x80x9cBGAxe2x80x9d) device package. FIG. 1 is a cross-sectional view of an example BGA device 10. The device 10 includes an integrated circuit 12 mounted upon a larger package substrate 14. Substrate 14 includes two sets of bonding pads: a first set of bonding pads 16 on an upper surface adjacent to integrated circuit 12 and a second set of bonding pads 18 arranged in a two-dimensional array across an underside surface. Integrated circuit 12 includes a semiconductor substrate 20 having multiple electronic components formed within a circuit layer 22 upon a front side surface of semiconductor substrate 20 during wafer fabrication. The electronic components are connected by electrically conductive interconnect lines to form an electronic circuit. Multiple I/O pads 24 are also formed within circuit layer 22. I/O pads 24 are typically coated with solder to form solder bumps 26.
The integrated circuit is attached to the package substrate using the controlled collapse chip connection method, which is also known as the C4(copyright) or flip-chip method. During the C4 mounting operation, solder bumps 26 are placed in physical contact with corresponding members of the first set of bonding pads 16. Solder bumps 26 are then heated long enough for the solder to reflow. When the solder cools, I/O pads 24 of integrated circuit 12 are electrically and mechanically coupled to the corresponding members of the first set of bonding pads 16 of the package substrate. After integrated circuit 12 is attached to package substrate 14, the region between integrated circuit 12 and package substrate 14 is filled with an under-fill material 28 to encapsulate the C4 connections and provide additional mechanical benefits.
Package substrate 14 includes one or more layers of signal lines that connect respective members of the first set of bonding pads 16 and the second set of bonding pads 18. Members of the second set of bonding pads 18 function as device package terminals and are coated with solder, forming solder balls 30 on the underside surface of package substrate 14. Solder balls 30 allow BGA device 10 to be surface mounted to an ordinary PCB. During PCB assembly, BGA device 10 is attached to the PCB by reflow of solder balls 30 just as the integrated circuit is attached to the package substrate.
The C4 mounting of integrated circuit 12 to package substrate 14 prevents physical access to circuit layer 22 for failure analysis and fault isolation. Thus, an alternative approach is to construct an electrically conductive probe that extends from the backside 40 of the substrate 20 to selected signal lines in the interconnect layer 22. The criteria for choosing the signal lines are based upon those signal lines that are expected to be at a certain signal level in accordance with a given test. As the density of components on the substrate 20 increases, it is becoming increasingly difficult to construct a probe that extends between the components. That is, there is an increasing risk that the probe may make contact with a component, for example, the drain region of a transistor, or otherwise interfere with the desired electrical characteristics of the component. Therefore, a semiconductor structure that addresses the aforementioned problems associated with flip-chip testing is desired.
Generally, the present invention relates to a semiconductor structure having an electrically conductive probe that extends from the back side of an integrated circuit through the substrate to a selected region in the substrate.
In one embodiment, the invention is a semiconductor structure that comprises: a substrate having a first surface and a second surface; an active region disposed in and at the second surface of the substrate; and an electrically conductive probe extending from the first surface of the substrate to the active region.
In another embodiment, the semiconductor structure comprises: a substrate having a first surface and a second surface; a transistor including source and drain regions disposed in and at the second surface of the substrate; a well region surrounding the source and drain regions; and an electrically conductive probe extending from the first surface of the substrate to the well region.
A plurality of probes are provided in another embodiment of the invention. The semiconductor structure comprises: a substrate having a first surface and a second surface; a plurality of transistors, each including respective source and drain regions disposed in and at the second surface of the substrate; a plurality of well regions surrounding selected respective pairs of the source and drain regions; and a plurality of conductive probes extending from the first side of the substrate to selected ones of the source, drain, and well regions.
A semiconductor structure having probes that are electrically coupled is provided in another embodiment. The structure comprises a substrate having a first surface and a second surface. A plurality of active regions are disposed in the substrate, and a plurality of electrically conductive probes extend from the first surface of the substrate to selected ones of the source, drain, and well regions. An electrically insulative layer is disposed on the first surface of the substrate and extends between one or more selected pairs of the probes, and one or more electrically conductive lines are disposed on the insulative layer and respectively couple the selected one or more pairs of probes.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.